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50 mhz to 2200 mhz quadrature modulator with integrated detector and vva adl5386 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features output frequency range: 50 mhz to 2200 mhz 1 db output compressio n: 11 dbm @ 350 mhz noise floor: ?160 dbm/hz @ 350 mhz sideband suppression: ?46 dbc @ 350 mhz carrier feedthrough: ?38 dbm @ 350 mhz 30 db of linear agc dynamic range @ 350 mhz single supply: 4.75 v to 5.5 v 40-lead, pb-free lfcsp_vq with exposed paddle applications radio-link infrastructures cable modem termination systems wireless/cellular infrastructure systems wireless local loops wimax/broadband wireless access systems general description the adl5386 is a quadrature modulator with unmatched integration levels for low intermediate frequency (if) and radio frequency (rf) transmitters within broadband wireless access systems, microwave radio links, cable modem termination systems, and cellular infrastructure equipment. the adl5386 operates over a frequency range of 50 mhz to 2200 mhz. its excellent phase accuracy and amplitude balance supports high data rate, complex modulation for next-generation communication infrastructure equipment. in addition, the adl5386 incorporates a standalone logarithmic power detector, as well as a voltage variable attenuator (vva). the attenuator has its own separate input and output pins for easy cascading with filters and buffer amplifiers. the wide dynamic range of the power detector and vva provides flexibility in the choice of the signal monitoring point in the transmitter system. the wide baseband input bandwidth of 700 mhz allows for either baseband drive or a drive from a complex if signal. typical applications are in if or direct-to-rf radio-link transmitters, cable modem termination systems, broadband wireless access systems, and cellular infrastructure equipment. the adl5386 takes signals from two differential baseband inputs and modulates them onto two carriers in quadrature with each other. the two internal carriers are derived from a single-ended, external local oscillator (lo) input signal at twice the frequency as the desired output. the output amplifier is designed to drive a 50 load. the adl5386 consists of two die, one fabricated using the analog devices, inc., advanced sige bipolar process, and the other using an external gaas process. the adl5386 is packaged in a 40-lead, pb-free lfcsp_vq with an exposed paddle. performance is specified over the ?40c to +85c range. a pb-free evaluation board is also available. functional block diagram ibbp ibbn qbbn qbbp loip loin atto atti modout comm tadj attcm attcm enbl nc vdet/vctl vset temp inhi inlo vpos vpos vref temperature sensor log detector iq mod bias 15db iv 17 14 20 25 33 34 26 6 7 4 3 9 22 21 10 12 35 23 36 38 37 39 24 8 12 29 30 adl5386 13 511 1618 15 28 19 27 3231 40 i v 07664-001 clpf quadrature phase splitter figure 1.
adl5386 rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? typical input and output impedances ...................................... 8 ? absolute maximum ratings ............................................................ 9 ? esd caution .................................................................................. 9 ? pin configuration and function descriptions ........................... 10 ? typical performance characteristics ........................................... 12 ? modulator .................................................................................... 12 ? voltage variable attentuator ..................................................... 16 ? detector ....................................................................................... 17 ? closed-loop agc mode........................................................... 18 ? circuit description ......................................................................... 19 ? overview ...................................................................................... 19 ? quadrature modulator section ................................................ 19 ? logarithmic detector ................................................................. 20 ? voltage variable attenuator (vva) ......................................... 20 ? basic connections .......................................................................... 21 ? open-loop power control mode ............................................ 21 ? power supply and grounding .................................................. 22 ? device enable and disable ........................................................ 22 ? baseband inputs ......................................................................... 22 ? lo input ...................................................................................... 22 ? agc mode .................................................................................. 22 ? setting the tadj resistor .......................................................... 24 ? using the detector in standalone measurement mode ........ 25 ? dac modulator interfacing ..................................................... 25 ? spectral products from harmonic mixing ............................. 27 ? lo generation using plls ....................................................... 27 ? transmit dac options ............................................................. 28 ? modulator/demodulator options ........................................... 28 ? evaluation board ............................................................................ 29 ? characterization setup .................................................................. 31 ? ssb setup ..................................................................................... 31 ? detector setup ............................................................................ 31 ? vva s-paramters setup ............................................................. 32 ? vva intermodulation test setup ............................................. 32 ? outline dimensions ....................................................................... 33 ? ordering guide .......................................................................... 33 ? revision history 1/09revision 0: initial version
adl5386 rev. 0 | page 3 of 36 specifications unless otherwise noted, v s = 5 v, t a = 25c, lo = ?7 dbm, i/q inputs = 1.4 v p-p diff erential sine waves in quadrature on a 500 mv dc bias, baseband frequency = 1 mhz, lo source and rf output load impedances are 50 . table 1. parameter conditions min typ max unit modulator dynamic characteristics operating frequency range 50 2200 mhz external lo frequency range external lo frequency is twice output frequency 100 4400 mhz output frequency = 50 mhz output power single (lower) si deband output 5.6 dbm modulator voltage gain ?1.3 db output p1db 10.8 dbm output return loss ?21 db carrier leakage unadjusted (nominal drive level) ?43 dbm at 85c after optimization at 25c ?63 dbm at ?40c after optimization at +25c ?63 dbm sideband suppression unadjusted (nominal drive level) ?48 dbc at 85c after optimization at 25c ?60 dbc at ?40c after optimization at +25c ?60 dbc quadrature error ?0.2 degrees i/q amplitude balance 0.05 db second harmonic (f lo ? (2 f bb )), p out = 5 dbm ?80 dbc third harmonic (f lo + (3 f bb )), p out = 5 dbm ?58 dbc output ip2 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 76 dbm output ip3 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 26 dbm noise floor 20 mhz offset from lo, all bb inputs at a bias of 500 mv ?159 dbm/hz output frequency = 140 mhz output power single (lower) si deband output 5.7 dbm modulator voltage gain ?1.2 db output p1db 11.1 dbm output return loss ?21 db carrier leakage unadjusted (nominal drive level) ?42 dbm at 85c after optimization at 25c ?62 dbm at ?40c after optimization at +25c ?62 dbm sideband suppression unadjusted (nominal drive level) ?57 dbc at 85c after optimization at 25c ?60 dbc at ?40c after optimization at +25c ?60 dbc quadrature error ?0.2 degrees i/q amplitude balance 0.05 db second harmonic (f lo ? (2 f bb )), p out = 5 dbm ?79 dbc third harmonic (f lo + (3 f bb )), p out = 5 dbm ?56 dbc output ip2 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 75 dbm output ip3 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 25 dbm noise floor 20 mhz offset from lo, all bb inputs at a bias of 500 mv ?160 dbm/hz output frequency = 350 mhz output power single (lower) si deband output 4 5.5 7 dbm modulator voltage gain ?1.4 db output p1db 11.1 dbm output return loss ?19 db carrier leakage unadjusted (nominal drive level) ?38 dbm at 85c after optimization at 25c ?58 dbm at ?40c after optimization at +25c ?58 dbm
adl5386 rev. 0 | page 4 of 36 parameter conditions min typ max unit sideband suppression unadjusted (nominal drive level) ?46 dbc at 85c after optimization at 25c ?57 dbc at ?40c after optimization at +25c ?57 dbc quadrature error ?0.5 degrees i/q amplitude balance 0.05 db second harmonic (f lo ? (2 f bb )), p out = 5 dbm ?76 dbc third harmonic (f lo + (3 f bb )), p out = 5 dbm ?53 dbc output ip2 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 74 dbm output ip3 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 25 dbm noise floor 20 mhz offset from lo, all bb in puts at a bias of 500 mv ?160 dbm/hz 20 mhz offset from lo, output power = ?5 dbm ?156 dbm/hz output frequency = 860 mhz output power single (lower) sideband output 3.8 5.3 6.8 dbm modulator voltage gain ?1.6 db output p1db 11.4 dbm output return loss ?15 db carrier leakage unadjusted (nominal drive level) ?37 dbm at 85c after optimization at 25c ?56 dbm at ?40c after optimization at +25c ?56 dbm sideband suppression unadjusted (nominal drive level) ?39 dbc at 85c after optimization at 25c ?55 dbc at ?40c after optimization at +25c ?55 dbc quadrature error ?0.9 degrees i/q amplitude balance 0.05 db second harmonic (f lo ? (2 f bb )), p out = 5 dbm ?72 dbc third harmonic (f lo + (3 f bb )), p out = 5 dbm ?49 dbc output ip2 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 73 dbm output ip3 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 25 dbm noise floor 20 mhz offset from lo, all bb inputs at a bias of 500 mv ?160 dbm/hz 20 mhz offset from lo, output power = ?5 dbm ?157 dbm/hz output frequency = 1450 mhz output power single (lower) si deband output 4.3 dbm modulator voltage gain ?2.6 db output p1db 10.6 dbm output return loss ?15 db carrier leakage unadjusted (nominal drive level) ?35 dbm at 85c after optimization at 25c ?50 dbm at ?40c after optimization at +25c ?50 dbm sideband suppression unadjusted (nominal drive level) ?43 dbc at 85c after optimization at 25c ?45 dbc at ?40c after optimization at +25c ?45 dbc quadrature error ?0.2 degrees i/q amplitude balance 0.03 db second harmonic (f lo ? (2 f bb )), p out = 5 dbm ?67 dbc third harmonic (f lo + (3 f bb )), p out = 5 dbm ?45 dbc output ip2 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 63 dbm output ip3 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 25 dbm noise floor 20 mhz offset from lo, all bb inputs at a bias of 500 mv ?160 dbm/hz
adl5386 rev. 0 | page 5 of 36 parameter conditions min typ max unit output frequency = 1900 mhz output power single (lower) si deband output 3.2 dbm modulator voltage gain ?3.7 db output p1db 9.2 dbm output return loss ?13 dbm carrier leakage unadjusted (nominal drive level) ?35 dbm at 85c after optimization at 25c ?53 dbm at ?40c after optimization at +25c ?53 dbm sideband suppression unadjusted (nominal drive level) ?30 dbc at 85c after optimization at 25c ?45 dbc at ?40c after optimization at +25c ?45 dbc quadrature error ?3 degrees i/q amplitude balance 0.02 db second harmonic (f lo ? (2 f bb )), p out = 5 dbm ?59 dbc third harmonic (f lo + (3 f bb )), p out = 5 dbm ?45 dbc output ip2 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 55 dbm output ip3 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 23 dbm noise floor 20 mhz offset from lo, all bb inputs at a bias of 500 mv ?160 dbm/hz 20 mhz offset from lo, output power = ?5 dbm ?156 dbm/hz output frequency = 2150 mhz output power single (lower) si deband output 2.5 dbm modulator voltage gain ?4.4 db output p1db 8.4 dbm output return loss ?11 db carrier leakage unadjusted (nominal drive level) ?35 dbm at 85c after optimization at 25c ?48 dbm at ?40c after optimization at +25c ?46 dbm sideband suppression unadjusted (nominal drive level) ?34 dbc at 85c after optimization at 25c ?45 dbc at ?40c after optimization at +25c ?45 dbc quadrature error ?1.2 degrees i/q amplitude balance 0.03 db second harmonic (f lo ? (2 f bb )), p out = 5 dbm ?56 dbc third harmonic (f lo + (3 f bb )), p out = 5 dbm ?48 dbc output ip2 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 53 dbm output ip3 f1 = 3.5 mhz, f2 = 4.5 mhz, p out = ?3 dbm per tone 21 dbm noise floor 20 mhz offset from lo, all bb inputs at a bias of 500 mv ?160 dbm/hz 20 mhz offset from lo, output power = ?5 dbm ?155 dbm/hz lo inputs pin loip and pin loin lo drive level characterization performed at typical level ?13 ?7 +2 dbm characterization performed at typical level (<140 mhz) ?7 ?7 +2 dbm input impedance 50 input return loss 350 mhz, loin ac-coupled to ground ?7 db baseband inputs pin ibbp, pin ibbn, pin qbbp, pin qbbn i and q input bias level 500 mv input bias current ?60 a bandwidth (0.1 db) f lo = 2 900 mhz, p out ?4 dbm 50 mhz bandwidth (3 db) f lo = 2 900 mhz, p out ?4 dbm 700 mhz
adl5386 rev. 0 | page 6 of 36 parameter conditions min typ max unit voltage variable attenuator pin vctl, pin atti, and pin atto, open-loop mode, attenuation control applied to vctl output frequency = 50 mhz insertion loss minimum attenuation, v vctl = 2 v 1.7 db attenuation range attenuation at v vctl = 2 v ? attenuation at v vctl = 0 v 37.8 db return loss 17 db input ip3 minimum attenuation, v vctl = 2 v, f = 1 mhz, input power = ?3 dbm per tone 36 dbm output frequency = 140 mhz insertion loss minimum attenuation, v vctl = 2 v 1.9 db attenuation range attenuation at v vctl = 2 v ? attenuation at v vctl = 0 v 37 db return loss 17 db input ip3 minimum attenuation, v vctl = 2 v, f = 1 mhz, input power = ?3 dbm per tone 36 dbm output frequency = 350 mhz insertion loss minimum attenuation, v vctl = 2 v 2.2 db attenuation range attenuation at v vctl = 2 v ? attenuation at v vctl = 0 v 26.2 db return loss 17 db input ip3 minimum attenuation, v vctl = 2 v, f = 1 mhz, input power = ?3 dbm per tone 35 dbm output frequency = 860 mhz insertion loss minimum attenuation, v vctl = 2 v 2.5 db attenuation range attenuation at v vctl = 2 v ? attenuation at v vctl = 0 v 21 db return loss 14 db input ip3 minimum attenuation, v vctl = 2 v, f = 1 mhz, input power = ?3 dbm per tone 35 dbm output frequency = 1900 mhz insertion loss minimum attenuation, v vctl = 2 v 3 db attenuation range attenuation at v vctl = 2 v ? attenuation at v vctl = 0 v 19 db return loss 13 db input ip3 minimum attenuation, v vctl = 2 v, f = 1 mhz, input power = ?3 dbm per tone 36 dbm output frequency = 2150 mhz insertion loss minimum attenuation, v vctl = 2 v 3.3 db attenuation range attenuation at v vctl = 2 v ? attenuation at v vctl = 0 v 17 db return loss 13 db input ip3 minimum attenuation, v vctl = 2 v, f = 1 mhz, input power = ?3 dbm per tone 35 dbm switching characteristics attcm (pin 14 and pin 17) = 1000 pf vctl response time frequency = 350 mhz, v vctl = 2 v to 0 v; measured from 50 % of v vctl to10% of rf envelope 125 ns frequency = 350 mhz, v vctl = 0 v to 2 v; measured from 50 % of v vctl to 90% of rf envelope 15 ns log detector in measurement mode, vdet/vctl is shorted to vset; in controller mode, the setpoint voltage is applied to vset; the cw input signal is applied at inhi f = 50 mhz r tadj = 22.1 k 1 db dynamic range t a = 25c 28 db slope 1 ?21 mv/db intercept 1 18.2 dbm vdet or vset voltage p in = ?10 dbm 0.59 v p in = ?30 dbm 1.01 v
adl5386 rev. 0 | page 7 of 36 parameter conditions min typ max unit f = 140 ghz r tadj = 22.1 k 1 db dynamic range t a = 25c 28 db slope 1 ?21.1 mv/db intercept 1 17.8 dbm vdet or vset voltage p in = ?10 dbm 0.59 v p in = ?30 dbm 1.01 v f = 350 mhz r tadj = 22.1 k 1 db dynamic range t a = 25c 26 db slope 1 ?21.3 mv/db intercept 1 17.1 dbm vdet or vset voltage p in = ?10 dbm 0.58 v p in = ?30 dbm 1.0 v f = 860 mhz r tadj = 22.1 k 1 db dynamic range t a = 25c 25 db slope 1 ?21.6 mv/db intercept 1 16.2 dbm vdet or vset voltage p in = ?10 dbm 0.57 v p in = ?30 dbm 1.00 v f = 1900 mhz r tadj = 22.1 k 1 db dynamic range t a = 25c 26 db slope 1 ?22.7 mv/db intercept 1 13.5 dbm vdet or vset voltage p in = ?10 dbm 0.54 v p in = ?30 dbm 0.99 v f = 2150 mhz r tadj = 22.1 k 1 db dynamic range t a = 25c 24 db slope 1 ?23.2 mv/db intercept 1 12.6 dbm vdet or vset voltage p in = ?10 dbm 0.53 v p in = ?30 dbm 0.99 v log detector output interface vdet vdet voltage swing v vset = 0 v, inhi = open, controller mode 2 v v vset = 2 v, inhi = open, controller mode 10 mv small signal bandwidth simulated, inhi = ?10 dbm, from clpf to vout >100 mhz output noise inhi = 2.2 ghz, C10 dbm, f noise = 100 khz, c clpf = open 73 nv/hz fall time input level = no signal to ?10 dbm, 90% to 10%, c clpf = 8 pf 42 ns input level = no signal to ?10 dbm, 90% to 10%, c clpf = 0.1 f 178 s rise time input level = ?10 dbm to no signal, 10% to 90%, c clpf = 8 pf 29 ns input level = ?10 dbm to no signal, 10% to 90%, c clpf = 0.1 f 174 s video bandwidth 15 mhz vset incremental input resistance p out = 0 dbm, agc mode, v vset = 0.9 v to 1 v 33,000 dv/di vset input bias current p out = 0 dbm, agc mode, v vset = 1 v 25 a tadj interface tadj input resistance tadj = 0.9 v, sourcing 50 a 13 k disable threshold voltage tadj = open v vpos ? 0.4 v temperature sensor output temp output voltage t a = 27.15c, 300k, r l = 1 m (after full warmup) 1.45 v temperature slope ?40c t a +85c, r l = 1 m 4.6 mv/c output impedance 1 k
adl5386 rev. 0 | page 8 of 36 parameter conditions min typ max unit enable input enbl input bias current enbl = 5 v 0.5 a enbl = 0 v ?0.7 a enbl high level (logic 1) 1.5 v enbl low level (logic 0) 0.4 v power supplies pin vpos voltage 4.75 5.5 v supply current enbl = high 230 245 ma in sleep mode, enbl = low and tadj = high 2.2 ma in detector disabled mode, enbl = high and tadj = high 215 ma 1 slope and intercept are determined by calculating the best-fit line between the power levels of ?33 dbm and ?10 dbm at the spe cified input frequency. typical input and output impedances unless otherwise noted, v s = 5 v, t a = 25c. all impedances are normalized to 50 . the effects of the test fixture are de-embedded up to the pins of the device. table 2. frequency (mhz) lo input impedance at 2 frequency mo dulator output impedance detector input impedance 50 1.393 ? j0.027 0.847 ? j0.016 28.463 ? j11.386 140 1.406 + j0.013 0.839 + j0.019 15.159 ? j15.234 350 1.441 + j0.039 0.82 + j0.065 4.661 ? j10.6 860 1.66 + j0.077 0.764 + j0.166 1.158 ? j4.58 1450 2.261 ? j0.304 0.799 + j0.231 0.567 ? j2.545 1900 1.436 ? j1.898 0.856 + j0.371 0.375 ? j1.866 2150 0.517 ? j1.446 0.862 + j0.51 0.308 ? j1.652
adl5386 rev. 0 | page 9 of 36 absolute maximum ratings table 3. parameter rating supply voltage, vpos 5.5 v ibbp, ibbn, qbbp, qbbn range 0 v to 2.0 v loip and loin 13 dbm internal power dissipation 1.4 w ja (exposed paddle soldered down) 38c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adl5386 rev. 0 | page 10 of 36 pin configuration and fu nction descriptions ibbp ibbn qbbn qbbp loip loin atto a tti modout comm tadj attcm attcm enbl nc vdet/vctl vset temp inhi inlo v pos v pos vref temperature sensor log detector iq mod bias 15db iv 17 14 20 25 33 34 26 6 7 4 3 9 22 21 10 12 35 23 36 38 37 39 24 8 12 29 30 adl5386 13 511 1618 15 28 19 27 32 31 40 i v 07664-002 clpf quadrature phase splitter notes 1. nc = no connect. 2. connect the exposed pad to ground via a low impedance path. figure 2. pin configuration table 4. pin function descriptions pin o. mnemonic description 1 inlo detector common. this pin should be ac-coupled to ground. 2 inhi detector input. when operating in agc mode, a portion of the signal at the output of the vva (or at the output of a subsequent stage) is coupled back to this input. the signal should be ac-coupled into inhi. to provide a 50 match at inhi, a 50 resistor should be conne cted between inhi and ground (with the ac-coupling capacitor placed between the resistor and the inhi pin). 3 vset setpoint input. setpoint input for controll er mode or feedback input for measurement mode. 4 clpf agc loop filter capacitor. the ground-referenced capacitor that is connected to this pin sets the loop bandwidth of the agc circuit. 5, 11, 13, 15, 16, 18, 19, 27, 28, 31, 32, 40 comm device common. connect these pins to the same low impedance ground plane. 6 vref attenuator control voltage reference. in agc mode, this pin should be left open. in open-loop mode, when the vva is being controlled externally, a 2 v reference voltage should be applied to this pin. 7 vdet/vctl detector output/vva control voltage input. when the vva is being controlled externally (open-loop mode), the attenuation is controlled by the external voltage applied to this pin. the vva control range is from 0 v (maximum attenuation) to 2 v (minimum attenuation). in this mode, vref (pin 6) should be tied to approximately 2 v. when the vva is being operated in agc mode, this pin is left open with the voltage on the pin representing the agc drive voltage to the vva. if the vva is not being used, the agc log amp can be used as a standalone detector by connecting this pin to vset. in this mode, the log amp output voltage is available at this pin. 8 temp temperature sensor output. this pin provides a standalone temperature sensor output voltage. at room temperature, the nominal output voltage is equal to 1.45 v. the slope of the output voltage is equal to 4.6 mv/c. 9 nc no connect. do not connect this pin. 10 modout rf output of iq modulator. single-ended, 50 inte rnally biased rf output. modout is generally ac-coupled to the input of the vva (either atti or atto). 12, 20 atti, atto vva rf input/output. atti is normally ac-coupled to mo dout. however, because the vva is completely reversible, modout can also drive atto with at ti operating as the vva output. 14, 17 attcm vva input/output common. these pins should be ac-coupled to ground. 21 to 23, 35 to 38 vpos power supply. positive supply voltage pins. all pins shou ld be connected to the same supply (vs). to ensure adequate external bypassing, connect a 0.1 f capacitor between each pin and ground.
adl5386 rev. 0 | page 11 of 36 pin no. mnemonic description 24 enbl iq modulator enable. the iq modulator is enabled by connecting this pin to vpos and is disabled by connecting enbl to ground. 25, 26, 29, 30 ibbp, ibbn, qbbn, qbbp differential in-phase and quadrature baseband inputs. these high impedance inputs should be dc-biased to 0.5 v. nominal characterized ac signal swing is 700 mv p-p on each pin, resulting in a differential drive of 1.4 v p-p on each input pair. these inputs are not self-biased and have to be externally biased. 33 loip local oscillator input. the local oscillator signal, at two t imes the output frequency, should be ac-coupled into this pin. 34 loin local oscillator common. this pin should be ac-coupled to ground. 39 tadj temperature compensation adjustment pin and detector enable/disable. this pin is primarily used to provide temperature compensation to the on-chip log amp based agc circuit. the correct compensation current is set by connecting a ground-referenced resistor to this pin. a value of 22.1 k is recommended for the frequencies over which the adl5386 is specified. the tadj pin can also be used to power down the detector section of the adl5386 by connecting it to vpos. the detector must be disabled when the modulator/vva is operating in open loop mode. 41 (epad) exposed pad (epad) connect the exposed pad to ground via a low impedance path.
adl5386 rev. 0 | page 12 of 36 typical performance characteristics modulator unless otherwise noted, v s = 5 v, t a = 25c, lo = ?7 dbm, i/q inputs = 1.4 v p-p differential sine waves in quadrature on a 500 mv dc bias, baseband frequency = 1 mhz, lo source and rf output load impedances are 50 . 14 13 12 11 10 9 8 7 6 5 4 3 2 1 50 550 1050 1550 2050 07664-003 ssb output power, output p1db (dbm) output frequency (mhz) v s = 5.5v v s = 5.0v v s = 4.75v ssb output power output p1db figure 3. single sideband (ssb) output power (p out ), output p1db vs. output frequency and power supply output p1db ssb output power 14 13 12 11 10 9 8 7 6 5 4 3 2 1 50 550 1050 1550 2050 07664-004 ssb output power, output p1db (dbm) output frequency (mhz) +85c +25c ?40c figure 4. single sideband (ssb) output power (p out ), output p 1 db vs. output frequency and temperature ?20 ?30 ?40 ?50 ?60 ?70 ?80 15 10 5 0 ?5 ?10 ?15 10 second-order distortion (dbc), third-order distortion (dbc), carrier feedthrough (dbm), sideband suppression (dbc) ssb output power (dbm) 0.1 1.0 differential baseband voltage (v p-p) ssb output power carrier feedthrough sideband suppression second-order distortion third-order distortion 07664-005 figure 5. second- and third-order dist ortion, carrier feedthrough, sideband suppression, and ssb output power vs . differential baseband voltage, output frequency = 350 mhz ?20 ?30 ?40 ?50 ?60 ?70 ?80 15 10 5 0 ?5 ?10 ?15 10 second-order distortion (dbc), third-order distortion (dbc), carrier feedthrough (dbm), sideband suppression (dbc) ssb output power (dbm) 0.1 1.0 differential baseband voltage (v p-p) ssb output power carrier feedthrough sideband suppression second-order distortion third-order distortion 07664-006 figure 6. second- and third-order dist ortion, carrier feedthrough, sideband suppression, and ssb output power vs . differential baseband voltage, output frequency = 860 mhz 90 80 70 60 50 40 30 20 10 0 50 550 1050 1550 2050 07664-007 output ip2 and ip3 (dbm) output frequency (mhz) oip3 oip2 +85c +25c ?40c figure 7. output ip2 and ip3 vs. output frequency and temperature ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 1000 baseband frequency response (db) bb frequency (mhz) 07664-008 figure 8. baseband frequency response normalized to response for 1 mhz bb signal, carrier frequency = 500 mhz
adl5386 rev. 0 | page 13 of 36 ? 20 ?30 ?40 ?50 ?60 ?70 ?80 07664-009 carrier feedthrough (dbm) 50 550 1050 1550 2050 output frequency (mhz) +85c +25c ?40c figure 9. carrier feedthrough distribution vs. output frequency and temperature 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 07664-010 carfrier feedthrough (dbm) output frequency (mhz) 50 550 1050 1550 2050 +85c +25c ?40c figure 10. carrier feedthrough distri bution at temperature extremes, after nulling to < ?65 dbm at t a = 25c vs. output frequency 0.010 0.008 0.006 0.004 0.002 0 ?0.002 ?0.004 ?0.006 ?0.008 ?0.010 output frequency (mhz) offset (v) 07664-011 i offset q offset 50 550 1050 1550 2050 figure 11. distribution of i offset an d q offset required to null carrier feedthrough vs. output frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 50 550 1050 1550 2050 07664-012 sideband suppression (dbc) output frequency (mhz) +85c +25c ?40c figure 12. sideband suppression vs . output frequency and temperature 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 50 550 1050 1550 2050 07664-013 sideband suppression (dbc) output frequency (mhz) +85c +25c ?40c figure 13. sideband suppr ession distribution at temperature extremes, after sideband suppression nulled to < ?50 dbc at t a = 25c vs. output frequency 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 94 93 92 91 90 89 88 87 86 50 550 1050 1550 2050 07664-014 iq amplitude offset (db) iq phase (degrees) output frequency (mhz) peak iq amplitude offset iq phase figure 14. distribution of peak q amplitude to null undesired sideband (peak i amplitude held constant at 0.7 v) and distribution of iq phase to null undesired sideband vs. output frequency
adl5386 rev. 0 | page 14 of 36 ?7 ?6 ? 20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?5 ?4 ?2 ?1 ?3 012 07664-015 carrier feedthrough (dbm) lo amplitude (dbm) 50mhz 350mhz figure 15. carrier feedthrough distribution vs. lo amplitude at 50 mhz and 350 mhz ?7 ?6 ? 20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?5 ?4 ?2 ?1 ?3 012 07664-016 sideband suppression (dbc) lo amplitude (dbm) 50mhz 350mhz figure 16. sideband suppression distribution vs. lo amplitude at 50 mhz and 350 mhz ? 20 ?30 ?40 ?50 ?60 ?70 100 sideband suppression (dbc) 1 10 baseband frequency (mhz) 07664-017 figure 17. sideband suppression vs. baseband frequency, output frequency = 350 mhz j2 j1 ?j1 ?j2 j0.5 ?j0.5 2250mhz s11 of loip s22 of mod output s11 of detector input 50mhz 100mhz 2250mhz 50mhz 4500mhz 07664-018 figure 18. modulator output impedan ce, lo input impedance and detector input impedance (unterminated) vs. frequency 0.5 1.0 1.5 2.0 2.5 loip frequency (ghz) return loss (db) 3.0 3.5 4.0 04 . 5 ?15 ?10 ?5 ?20 0 07664-019 figure 19. lo port input return loss vs. loip frequency 30 25 20 15 10 5 0 07664-020 number of parts offset from output frequency (dbm/hz at 20mhz) ?158.2 ?158.0 ?157.8 ?157.6 ?157.4 ?157.2 ?157.0 ?156.8 ?156.6 ?156.4 ?156.2 ?156.0 figure 20. 20 mhz offset noise floor distribution, output frequency = 360 mhz, p out = ?5 dbm, qpsk carrier, symbol rate = 3.84 msps
adl5386 rev. 0 | page 15 of 36 35 30 25 20 15 10 5 0 07664-021 number of parts offset from output frequency (dbm/hz at 20mhz) ?156.0 ?155.8 ?155.6 ?155.4 ?155.2 ?155.0 ?154.8 ?154.6 ?154.4 ?154.2 ?154.0 figure 21. 20 mhz offset noise floo r distribution, output frequency = 860 mhz, p out = ?5 dbm, 64 qam carrier, symbol rate = 5 msps power supply current with modulator disabled and detector enabled ?40 250 225 200 175 150 125 100 75 26 24 22 20 18 16 14 12 25 temperature (c) modulator supply current (ma) detector supply current (ma) 85 power supply current with modulator enabled and detector disabled v s = 5.5v v s = 5.0v v s = 4.75v 07664-022 figure 22. power supply current vs . temperature and supply voltage
adl5386 rev. 0 | page 16 of 36 voltage variable attentuator unless otherwise noted, v s = 5 v, t a = 25c. ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 attenuation and return loss (db) input ip3 and input ip2 (db m ) v vctl (v) input ip2 return loss attenuation input ip3 07664-023 +85c +25c ?40c figure 23. iip3, iip2, attenuation, and return loss vs. v vctl voltage and temperature at 140 mhz ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 attenuation and return loss (db) input ip3 and input ip2 (db m ) v vctl (v) attenuation 07664-024 +85c +25c ?40c input ip2 return loss input ip3 figure 24. iip3, iip2, attenuation, and return loss vs. v vctl voltage and temperature at 350 mhz ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 attenuation and return loss (db) input ip3 and input ip2 (db m ) v vctl (v) return loss attenuation input ip3 07664-025 +85c +25c ?40c input ip2 figure 25. iip3, iip2, attenuation, and return loss vs. v vctl voltage and temperature at 860 mhz ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 attenuation and return loss (db) input ip3 and input ip2 ( d b m ) v vctl (v) return loss attenuation input ip3 07664-026 +85c +25c ?40c input ip2 figure 26. iip3, iip2, attenuation, and return loss vs. v vctl voltage and temperature at 1450 mhz ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 attenuation and return loss (db) input ip3 and input ip2 ( d b m ) v vctl (v) return loss 07664-027 +85c +25c ?40c input ip2 input ip3 attenuation figure 27. iip3, iip2, attenuation, and return loss vs. v vctl voltage and temperature at 1900 mhz ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 attenuation and return loss (db) input ip3 and input ip2 ( d b m ) v vctl (v) return loss attenuation 07664-028 +85c +25c ?40c input ip2 input ip3 figure 28. iip3, iip2, attenuation, and return loss vs. v vctl voltage and temperature at 2150 mhz
adl5386 rev. 0 | page 17 of 36 detector unless otherwise noted, v s = 5 v, t a = 25c. 1.50 1.25 1.00 0.75 0.50 0.25 0 3 2 1 0 ?1 ?2 ?3 ?45 ?25 ?35 ?15 ?5 5 07664-029 v vdet / v vset (v) power error (db) p in (dbm) +85c +25c ?40c figure 29. v vdet /v vset voltage and log conformanc e vs. input amplitude at 350 mhz, r tadj = 22.1 k 1.50 1.25 1.00 0.75 0.50 0.25 0 3 2 1 0 ?1 ?2 ?3 ?45 ?25 ?35 ?15 ?5 5 07664-030 v vdet / v vset (v) power error (db) p in (dbm) +85c +25c ?40c figure 30. v vdet /v vset voltage and log conformanc e vs. input amplitude at 860 mhz, r tadj = 22.1 k 1.50 1.25 1.00 0.75 0.50 0.25 0 3 2 1 0 ?1 ?2 ?3 ?45 ?25 ?35 ?15 ?5 5 07664-031 v vdet /v vset (v) power error (db) p in (dbm) +85c +25c ?40c figure 31. v vdet /v vset voltage and log conformance vs. input amplitude at 1450 mhz, r tadj = 22.1 k 1.50 1.25 1.00 0.75 0.50 0.25 0 3 2 1 0 ?1 ?2 ?3 ?45 ?25 ?35 ?15 ?5 5 07664-032 v vdet /v vset (v) power error (db) p in (dbm) +85c +25c ?40c figure 32. v vdet /v vset voltage and log conformance vs. input amplitude at 2150 mhz, r tadj = 22.1 k
adl5386 rev. 0 | page 18 of 36 closed-loop agc mode unless otherwise noted, v s = 5 v, t a = 25c, lo = ?7 dbm, i/q inputs = 1.4 v p-p differential sine waves in quadrature on a 500 mv dc bias, baseband frequency = 1 mhz, lo source and rf output load impedances are 50 . for agc mode characterization setup, refer to figure 42 . ?4 ?3 ?2 ?1 0 1 2 3 4 ?35 ?30 ?25 ?20 ?15 ?10 5 0 5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 error (db) p out (dbm) v vset (v) ? 07664-033 +85c +25c ?40c figure 33. p out and error vs. v vset at 140 mhz ?4 ?3 ?2 ?1 0 1 2 3 4 ?35 ?30 ?25 ?20 ?15 ?10 5 0 5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 error (db) p out (dbm) v set (v) ? 07664-034 +85c +25c ?40c figure 34. p out and error vs. v vset at 350 mhz ?4 ?3 ?2 ?1 0 1 2 3 4 ?35 ?30 ?25 ?20 ?15 ?10 5 0 5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 error (db) p out (dbm) v vset (v) ? 07664-035 +85c +25c ?40c figure 35. p out and error vs. v vset at 860 mhz ?4 ?3 ?2 ?1 0 1 2 3 4 ?35 ?30 ?25 ?20 ?15 ?10 5 0 5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 error (db) p out (dbm) v vset (v) ? 07664-036 +85c +25c ?40c figure 36. p out and error vs. v vset at 1450 mhz ?4 ?3 ?2 ?1 0 1 2 3 4 ?35 ?30 ?25 ?20 ?15 ?10 5 0 5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 error (db) p out (dbm) v vset (v) ? 07664-037 +85c +25c ?40c figure 37. p out and error vs. v vset at 1900 mhz ?4 ?3 ?2 ?1 0 1 2 3 4 ?35 ?30 ?25 ?20 ?15 ?10 5 0 5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 error (db) p out (dbm) v vset (v) ? 07664-038 +85c +25c ?40c figure 38. p out and error vs. v vset at 2150 mhz
adl5386 rev. 0 | page 19 of 36 circuit description ibbp ibbn qbbn qbbp loip loin atto atti modout comm tadj attcm attcm enbl nc vdet/vctl vset temp inhi inlo v pos vpos vref temperature sensor log detector iq mod bias 15db iv 17 14 20 25 33 34 26 6 7 4 3 9 22 21 10 12 35 23 36 38 37 39 24 8 12 29 30 adl5386 13 511 1618 15 28 19 27 3231 40 i v 07664-039 clpf quadrature phase splitter figure 39. block diagram overview the adl5386 consists of three sections: a quadrature modulator, a logarithmic detector, and a voltage variable attenuator (vva). the modulator section contains the circuitry for the following functions: ? local oscillator (lo) interface ? baseband voltage-to-current (v-to-i) converter ? mixers ? differential-to-single-ended (d-to-s) amplifier ? temperature sensor and bias circuit the detector section contains the logarithmic detector and amplifiers interfacing to the vset input and vdet output. the variable attenuator section consists of a pi network of phemts and resistors implemented on a gaas die separate from the silicon die where the rest of the circuits reside. a detailed block diagram of the device is shown in figure 39 . quadrature modulator section the lo interface generates two lo signals at 90 of phase difference to drive two mixers in quadrature. baseband signals are converted into currents by the v-to-i converters that feed into the two mixers. the outputs of the mixers are combined in the differential-to-single-ended amplifier, which provides a 50 output interface. reference currents to each section are generated by the bias circuit. a detailed description of each section follows. lo interface the lo interface consists of a buffer amplifier followed by a pair of frequency dividers that generate two carriers at half the input frequency and in quadrature with each other. each carrier is then amplified and amplitude-limited to drive the double- balanced mixers. v-to-i converter the differential baseband input voltages that are applied to the baseband input pins are fed to a pair of common-emitter, voltage- to-current converters. the output currents then modulate the two half-frequency lo carriers in the mixer stage. mixers the adl5386 has two double-balanced mixers: one for the in-phase channel (i channel) and one for the quadrature channel (q channel). these mixers are based on the gilbert cell design of four cross-connected transistors. the output currents from the two mixers are summed together in the resistor-inductor loads in the d-to-s amplifier. d-to-s amplifier the output d-to-s amplifier consists of two emitter followers driving a totem-pole output stage. output impedance is established by the emitter resistors in the output transistors. the output of this stage connects to the output (vout) pin. bias circuits a band gap based bias circuit provides proportional-to-absolute temperature as well as temperature stable reference currents for the different circuits in the modulator section. the enbl input controls the operation of this bias circuit. when enbl is pulled to a low level, the bias references are turned off, and the whole modulator section is turned off as a result. a voltage that is proportional to the absolute temperature of the circuit is also available at the temp pin. a separator bias circuit provides the reference currents as well as the reference voltages for the detector and voltage variable attenuator sections. this bias circuit can also be disabled by pulling the tadj pin high, which in turn shuts down the detector section.
adl5386 rev. 0 | page 20 of 36 logarithmic detector the design of the log detector is similar to that of the ad8317 standalone log detector device, where the log function is generated by a series of limiting amplifiers and detectors. the output current from this log detector is compared with that from a voltage-to-current converter connected to the vset input. any net difference between these two currents is pumped into an on-chip integrating capacitor that is generally augmented by additional off-chip capacitance. the voltage on the integrating capacitor is amplified and produces an output error voltage that is generally used to adjust the attenuation of the voltage variable attenuator until the vset current and the current from the log detector are balanced. voltage variable attenuator (vva) the vva is implemented on a gaas die separate from the silicon die where the modulator and detector reside. the vva is formed by phemts and resistors connected in a pi network to provide the attenuator function. the gate source bias on the phemts are controlled by the voltages on the vref and vdet/ vctl pins, resulting in different attenuation between atti and atto as the voltage at vdet/vctl is varied. the resistance in the shunt paths between atti and atto to attcm var y in the opposite manner as the paths between atti and atto to maintain good return loss through different attenuation levels.
adl5386 rev. 0 | page 21 of 36 basic connections open-loop power control mode figure 41 shows the basic connections for operating the adl5386 when the voltage variable attenuator (vva) is driven from an external voltage source and not from the built-in agc circuit. in this mode, the inputs to the rf detector should be both ac-coupled to ground. the tadj pin is tied to the supply, disabling the unused detector and reducing the current consumption by approximately 15 ma. the iq modulator is enabled by pulling the enbl pin high. the output of the modulator is ac-coupled to the input of the vva (pin atti). the vva is bidirectional; therefore, the modulator can also be configured to drive atto and to take the final output at atti. the attenuation of the vva is controlled by the voltages on pin vref and pin vdet/vctl. vref should be tied to a low impedance external voltage of 2 v. this voltage can be conveniently derived from the supply voltage using a pair of resistors, but this voltage must then be buffered with an op amp to prevent bias current related voltage drops. with vref set to 2 v, a variable voltage between 0 v and 2 v on vdet/vctl sets the attenuation. maximum attenuation is achieved when v vdet /v vctl = 0 v, and minimum attenuation is achieved when v vdet /v vctl = 2 v. figure 40 shows a plot of p out vs. the control voltage (applied to the vdet/vctl pin) at 350 mhz when the modulator is driven by 1 v p-p sine and cosine signals on its baseband inputs and a 2 lo of 700 mhz. in this mode, the detector cannot be used in any kind of standalone mode because its output pin (vdet/vctl) is used as an input. ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 p out (dbm) v vdet /v vctl (v) 07664-040 figure 40. p out vs. v vdet /v vctl at 350 mhz for open-loop power control mode c3 1000pf c4 1000pf v p +5v c1 0.1f c12 lo in ip temp qp qn attenuation control 0v to 2v vp +5v attout c19 1000pf c10 c11 1000pf 1000pf 1000pf c2 0.1f c14 0.1f c5 0.1f c6 0.1f c13 0.1f ibbp ibbn qbbn qbbp loip loin atto atti modout comm clpf attcm attcm enbl nc vdet/vctl vset temp inhi tadj inlo vpos vpos vpos vref temperature sensor log detector iq mod bias 15db 4x 17 14 20 25 33 34 26 6 7 4 3 9 22 21 10 12 35 23 36 38 37 39 24 8 12 29 30 adl5386 13 511 1618 15 28 19 27 3231 40 i v 07664-041 quadrature phase splitter 2v c7 0.1f figure 41. basic connections for open-loop power control mode
adl5386 rev. 0 | page 22 of 36 power supply and grounding the vpos supply pins should be connected to a common 5 v supply. this supply can vary from 4.75 to 5.5 v. the power supply pins should be adequately decoupled using 0.1 f capacitors located close to each pin. adjacent pins can share decoupling capacitors, as shown in figure 41 . the comm ground pins should be connected to a common low impedance ground plane. the exposed paddle on the underside of the package is also soldered to a low thermal and electrical impedance ground plane. if the ground plane spans multiple layers on the circuit board, the layers should be stitched together with nine vias under the exposed paddle. the analog devices, an-772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp), discusses the thermal and electrical grounding of the lfcsp in detail. device enable and disable the iq modulator section can be enabled or disabled by pulling the enbl pin high or low, respectively. the detector section of the circuit can be disabled by pulling the tadj pin high. baseband inputs the baseband inputs, qbbp, qbbn, ibbp, and ibbn, must be driven from a differential source. the nominal drive level of 1.4 v p-p differential (700 mv p-p on each pin) is biased to a common-mode level of 500 mv dc. this drive level generates an output power level (at modout) of between 2 dbm and 6 dbm based on output frequency. the dc common-mode bias level for the baseband inputs can range from 400 mv to 600 mv. this results in a reduction in the usable input ac swing range. the nominal dc bias of 500 mv allows for the largest ac swing, limited on the bottom end by the adl5386 input range and on the top end by the output compliance range on most analog devices dacs. lo input a single-ended lo signal is applied to the loip pin through an ac coupling capacitor. a square wave or a sine wave can be used to drive the lo port. the recommended lo drive power is ?7 dbm. an lo power level of ?7 dbm is the minimum level that should be used for output frequencies below 140 mhz (f lo 280 mhz). at output frequencies above 140 mhz, the lo power can be reduced to ?13 dbm. the lo return pin, loin, should be ac-coupled to ground though a low impedance path. the nominal lo drive of ?7 dbm can be increased to up to +2 dbm. the effect of lo power on sideband suppression and carrier feedthrough is shown in figure 15 and figure 16 . agc mode the on-board log amp power detector of the adl5386 can be used to implement an automatic output power control (commonly referred to as agc) loop that effectively linearizes the transfer function of the vva. to implement this mode, a number of circuit modifications are necessary. a portion of the output signal of the vva is coupled back to the input of the log amp detector. this can be done with a power splitter or with a directional coupler as shown in figure 42 . the coupling factor or power split ratio should be set so that the detector never sees a power level that is greater than about ?10 dbm (the transfer function of the detector loses some linearity above this level). in the example shown in figure 42 , a maximum output power from the vva/modulator of +3 dbm is desired. a directional coupler with a coupling factor of approximately +15 db drops this level down to ?12 dbm at the input of the detector. the input signal to the detector produces a current that is drawn from the summing node (pin clpf) into the detector block. a setpoint voltage that is applied to the vset pin is converted into a current that is pumped into the summing node. if these two currents are not equal, the net current flows into or out of the clpf capacitor on pin 4. this changes the voltage on the clpf node that in turn changes the voltage on the vdet/vctl pin. this pin is internally connected to the attenuation control pin of the vva. therefore, the attenuation control voltage on pin 7 (vdet/vctl) increases or decreases until the i set and i det currents match. when this equilibrium is reached, the voltage on clpf (and thereby on the control voltage node of the vva) is held steady.
adl5386 rev. 0 | page 23 of 36 c3 1000pf c4 1000pf v p +5v c1 0.1f c12 lo in ip temp qp qn output power setpoint 0.7v to 1.5v c19 1000pf c10 c11 1000pf 1000pf 1000pf c2 0.1f c14 0.1f c13 0.1f ibbp ibbn qbbn qbbp loip loin atto atti modout comm clpf attcm attcm enbl nc vdet/vctl vset temp inhi tadj inlo vpos c7 0.1f vpos vpos quadrature phase splitter temperature sensor log detector iq mod bias 15db 4x 17 14 20 25 33 34 26 6 7 4 3 9 22 21 10 12 35 23 36 38 37 39 24 8 12 29 30 adl5386 13 511 1618 15 28 19 27 32 31 40 i v 07664-042 c6 0.1f c5 0.1f attout 50? r4 22.1k ? directional coupler p outmax = 3dbm r8 49.9 ? vref frequency 140mhz 350mhz 860mhz 1450mhz 1900mhz 2150mhz 0.2db 0.43db 0.77db 0.8db 0.77db 0.88db 15db 15.51db 13.68db 14.33db 15.2db 15.97db coupler insertion loss coupling factor figure 42. basic connections for agc mode
adl5386 rev. 0 | page 24 of 36 figure 43 shows the resulting transfer function of the agc loop, that is, output power (on atto) vs. setpoint voltage (on vset) at 350 mhz. figure 43 shows a linear-in-db relationship between p out and v vset over at least 25 db. it also includes a plot of the linearity of the transfer function in db. the linearity is calculated by measuring the slope and intercept of the transfer function using the v vset and p out data between v vset levels of 0.7 and 1 v. this yields an idealized transfer function of p out_ideal = slope ( v vset ? intercept) ?4 ?3 ?2 ?1 0 1 2 3 4 ?35 ?30 ?25 ?20 ?15 ?10 5 0 5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 error (db) p out (dbm) v vset (v) ? 07664-043 +85c +25c ?40c figure 43. p out vs. v vset transfer function in agc mode (1 v p-p differential baseband input voltage on i and q) the error in decibels is given by error (db) = ( p out ? p out_ideal )/ slope the relationship between the input level of the detector and the voltage on v vset follows from the nominal transfer function of the detector when operating in measurement mode (vset is connected directly to vdet). figure 44 shows the measurement mode relationship between the detector input level and the output voltage at 350 mhz. figure 44 shows that an input level of ?12 dbm produces an output of 0.6 v. in agc mode, a setpoint voltage of 0.6 v causes the loop to adjust until the detector input level is ?12 dbm. remembering the coupling factor of the directional coupler, the ?12 dbm level at the detector corresponds to a power level of approximately +3 dbm at the output of the vva. therefore, with a 15 db coupling factor, a setpoint voltage of 0.6 produces an output power from the vva of 3 dbm, as shown in figure 43 . in general, the loop should be designed with a level of attenuation between atto and inhi (detector input) that results in the detector always seeing a power level that is within its linear operating range. because the power detector has a linear input range that is larger than the attenuation range of the vva this is generally achievable. in addition, it is desirable to map the desired vva output power range into the detectors region of maximum linearity. in the example shown, where a maximum output power of +3 dbm is desired, the input range to the detector is ?12 dbm to ?44 dbm. notice how the degraded linearity of the detector below ?40 dbm (see figure 44 ) can also be observed in the closed-loop transfer function at output power levels below ?25 dbm ( figure 43 ). ?4 ?3 ?2 ?1 0 1 2 3 4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 v vout (v) error (db) p in (dbm) v out (v) error (db) 07664-044 figure 44. measurement mode relationship between v vout /v vset and detector input power at 350 mhz setting the tadj resistor the primary component of the temperature variation of the v vout /v vset voltage and the detector rf input is the drift of the intercept. this temperature drift can be compensated by connecting a resistor between tadj (pin 39) and ground. the optimum resistance value for the frequencies at which the adl5386 is characterized has been experimentally determined to be 22.1 k. note that the accuracy specifications of the detector and performance plots assume that this resistance is in place.
adl5386 rev. 0 | page 25 of 36 using the detector in standalone measurement mode the on-board log detector of the adl5386 can be used in measurement mode, that is, where an rf signal is applied to the inhi pin of the detector, and an output voltage, proportional to the log of this input signal, is provided at the vdet output. in this mode, short vdet to vset and ac couple the atti, atto, and attcm pins to ground. note that the vva cannot be used because the vva control voltage shares a common pin with the output of the detector. table 5 summarizes the required configuration changes for the three operating modes discussed. dac modulator interfacing the adl5386 is designed to interface with minimal components to members of the analog devices family of digital-to-analog converters (dacs). these dacs feature an output current swing from 0 ma to 20 ma, and the interface described in this section can be used with any dac that has a similar output. table 5. configuring operating modes mode inhi vset vdet/vctl vref enbl modout atti atto agc ac couple to atto via directional coupler externally apply 0.5 v to 1.4 v open open high ac couple to atti ac couple to modout rf output open loop 1 ac couple to gnd open externally apply 0 v to 2 v externally apply 2 v high ac couple to atti ac couple to modout rf output standalone detector ac couple to modout or other rf signal connect to vdet connect to vset open high rf output, ac-coupled ac couple to gnd ac couple to gnd 1 tie tadj to vpos. c3 1000pf c4 1000pf v p +5v c1 0.1f c30 lo in ip temp qp qn c10 c11 1000pf 1000pf 1000pf 1000pf 1000pf c2 0.1f c14 0.1f c13 0.1f ibbp ibbn qbbn qbbp loip loin atto atti modout comm attcm attcm enbl nc temp inhi inlo vpos vpos vpos vref temperature sensor dtin log detector iq mod bias 15db 4x 17 14 20 25 33 34 26 6 7 4 3 9 22 21 10 12 35 23 36 38 37 39 24 8 12 29 30 adl5386 13 511 1618 15 28 19 27 3231 40 i v 0 7664-045 quadrature phase splitter tadj c6 0.1f c5 0.1f r8 49.9 ? r4 22.1k ? clpf vdet vdet/vctl vset c7 0.1f c31 c20 mod out figure 45. connections for operating the detector in standalone mode
adl5386 rev. 0 | page 26 of 36 driving the adl5386 with an analog devices txdac? an example of the interface using the ad9788 txdac is shown in figure 46 . the baseband inputs of the adl5386 require a dc bias of 500 mv. the average output current on each of the outputs of the ad9788 is 10 ma. therefore, a single 50 resistor to ground from each of the dac outputs results in an average current of 10 ma flowing through each of the resistors, thus producing the desired 500 mv dc bias for the inputs to the adl5386. 07664-046 rbip 50? rbin 50? 25 26 ibbn ibbp txdac adl5386 rbqn 50? rbqp 50? 29 30 out1_n out1_p out2_p out2_n qbbp qbbn figure 46. interface between ad9788 and adl5386 with 50 resistors to ground to establish the 500 mv dc bi as for the adl5386 baseband inputs the ad9788 output currents source from 0 ma to 20 ma. with the 50 resistors in place, the ac voltage swing going into the adl5386 baseband inputs ranges from 0 v to 1 v. a full-scale sine wave out of the ad9788 can be described as a 1 v p-p single- ended (or 2 v p-p differential) sine wave with a 500 mv dc bias. the ad9788 also has the capability of easily compensating for gain, offset, and phase mismatch in the iq signal path; therefore, optimizing performance of the adl5386. limiting the ac swing there are situations in which it is desirable to reduce the ac voltage swing for a given dac output current. to reduce the ac voltage swing, add an additional resistor to the interface. this resistor is placed in shunt between each side of the differential pair, as shown in figure 47 . it has the effect of reducing the ac swing without changing the dc bias already established by the 50 resistors. 07664-047 rbip 50? rbin 50? ibbn ibbp txdac adl5386 rbqn 50? rbqp 50? rsli 100? rslq 100 ? qbbp qbbn 25 26 29 30 out1_n out1_p out2_p out2_n figure 47. ac voltage swing reduction through introduction of shunt resistor between differential pair the value of this ac voltage swing-limiting resistor is chosen based on the desired ac voltage swing. figure 48 shows the relationship between the swing-limiting resistor and the peak-to-peak ac swing that it produces when 50 bias-setting resistors are used. 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 100 1000 10000 07664-048 differential swing (v p-p) r l ( ? ) figure 48. relationship between ac swing-limiting resistor and peak-to-peak voltage swing with 50 bias-setting resistors filtering when driving a modulator from a dac, it is necessary to introduce a low-pass filter between the dac and the modulator to reduce the dac images. the interface for setting up the biasing and ac swing lends itself well to the introduction of such a filter. the filter can be inserted between the dc bias setting resistors and the ac swing-limiting resistor, thus establishing the input and output impedances for the filter. a filter example is shown in figure 49 . adl5386 1/2 ad9788 i channel 50? 67.5pf 50? 67.5pf 156.9pf 156.9pf 124.7pf 124.7pf 50? line 50? line 100 ? line 0 ? 100 ? line 317.4nh 372.5nh 317.4nh 372.5nh 0 ? 200 ? ibbp ibbn 1/2 ad9788 q channel 50? 67.5pf 50? 67.5pf 156.9pf 156.9pf 124.7pf 124.7pf 50? line 50? line 100 ? line 0 ? 100 ? line 317.4nh 372.5nh 317.4nh 372.5nh 0 ? 200 ? qbbp qbbn 07664-050 figure 49. 39 mhz, 5-pole chebychev filter with in-band ripple of 0.1 db for a 155 msps, 128 qam transmitter
adl5386 rev. 0 | page 27 of 36 spectral products from harmonic mixing for broadband applications, such as cable tv head-end modulators, special attention must be paid to harmonics of the lo. figure 50 shows the level of these harmonics (out to 3 ghz) as a function of the output frequency from 125 mhz to 1000 mhz, in a single-sideband (ssb) test configuration, with a baseband signal of 1 mhz and a ssb level of approximately 0 dbm. to read this plot correctly, first pick the output frequency of interest on the trace called p out . the associated harmonics can be read off the harmonic traces at multiples of this frequency. for example, at an output frequency of 500 mhz, the fundamental power is 0 dbm. the power of the second (p 2fc ? bb ) and third (p 3fc + bb ) harmonics is ?57 dbm (at 1000 mhz) and ?11 dbm (at 1500 mhz), respectively. of particular importance are the products from odd harmonics of the lo, generated from the switching operation in the mixers. for cable tv operation at frequencies above approximately 500 mhz, these harmonics fall out of the band and can be filtered by a fixed filter. however, as the frequency drops below 500 mhz, these harmonics start to fall close to or inside the cable band. this calls for either limitation of the frequency range to above 500 mhz or the use of a switchable filter bank to block in-band harmonics at low frequencies. ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 200 300 400 500 600 700 800 900 1000 p out , p harmonic ( d b m ) output frequency (mhz) p 4lo + bb p out p 3lo + bb p 5lo ? bb p 7lo + bb p 2lo ? bb p 6lo ? bb 07664-049 figure 50. spectral components for output frequencies from 125 mhz to 1000 mhz lo generation using plls analog devices has a line of plls that can be used for generating the lo signal. table 6 lists the plls together with their maximum frequency and phase noise performance. table 6. pll selection table model frequency f in (mhz) at 1 khz phase noise dbc/hz, 200 khz pfd adf4002 400 ?103 @ 400 mhz adf4106 6000 ?93 @ 900 mhz adf4110 550 ?91 @ 540 mhz adf4111 1200 ?87@ 900 mhz adf4112 3000 ?90 @ 900 mhz adf4113 4000 ?91 @ 900 mhz adf4116 550 ?89 @ 540 mhz adf4117 1200 ?87 @ 900 mhz adf4118 3000 ?90 @ 900 mhz the adf4360-x comes as a family of chips, with nine operating frequency ranges. one can be chosen depending on the local oscillator frequency required. while the use of the integrated synthesizer may come at the expense of slightly degraded noise performance from the adl5386, it can be a cheaper alternative to a separate pll and vco solution. table 7 shows the options available. an up-to-date list of available plls can be found at www.analog.com/pll . table 7. adf4360-x family operating frequencies model output frequency range (mhz) adf4360-0 2400 to 2725 adf4360-1 2050 to 2450 adf4360-2 1850 to 2150 adf4360-3 1600 to 1950 adf4360-4 1450 to 1750 adf4360-5 1200 to 1400 adf4360-6 1050 to 1250 adf4360-7 350 to 1800 adf4360-8 65 to 400 adf4360-9 1.1 to 200 (using auxiliary dividers)
adl5386 rev. 0 | page 28 of 36 transmit dac options the ad9788 recommended in the previous sections is by no means the only dac that can be interfaced with the adl5386. there are other appropriate dacs depending on the level of performance required. table 8 lists the dual txdacs that analog devices offers for use in transmitter applications with the adl5386. table 8. dual txdac selection table part no. resolution (bits) output update rate (msps) ad9114 / ad9115 / ad9116 / ad9117 8, 10, 12, 14 125 ad9741 / ad9743 / ad9745 / ad9746 / ad9747 8, 10, 12, 14, 16 250 ad9780 / ad9781/ ad9783 12, 14, 16 500 ad9776 a/ ad9778 a/ ad9779 a 12, 14, 16 1000 ad9785 / ad9787/ ad9788 12,14, 16 800 all dacs listed have nominal bias levels of 0.5 v and use the same dac-modulator interface shown in figure 46 . modulator/demodulator options table 9 lists other analog devices modulators and demodulators. table 9. modulator/demodulator options part no. modulator/ demodulator frequency range (mhz) comments ad8345 modulator 140 to 1000 ad8346 modulator 800 to 2500 ad8349 modulator 700 to 2700 adl5390 modulator 20 to 2400 external quadrature adl5370 modulator 300 to 1000 adl5371 modulator 500 to 1500 adl5372 modulator 1500 to 2500 adl5373 modulator 2300 to 3000 adl5374 modulator 3000 to 4000 adl5375 modulator 400 to 6000 ad8347 demodulator 800 to 2700 ad8348 demodulator 50 to 1000 adl5382 demodulator 700 to 2700 adl5387 demodulator 50 to 2000 adl5590 modulator 869 to 960 adl5591 modulator 1805 to 1990 ad8340 vector modulator 700 to 1000 ad8341 vector modulator 1500 to 2400
adl5386 rev. 0 | page 29 of 36 evaluation board a populated, rohs-compliant adl5386 evaluation board is available. the adl5386 has an exposed paddle underneath the package, which is soldered to the board. c15 open r16 0 ? r5 0 ? 0 ? r6 c16 open r27 open r29 open r17 0 ? r18 0 ? r28 open r24 open r26 open r19 0 ? r25 open r20 0 ? c3 1000pf c4 1000pf v p c1 0.1f c30 1000pf c10 1000pf c11 1000pf lo in ip temp qp qn c2 0.1f c14 0.1f c13 0.1f ibbp ibbn qbbn qbbp loip loin atto atti modout comm attcm attcm enbl nc temp inhi inlo vpos vpos vpos vref temperature sensor dtin log detector iq mod bias 15db iv 17 14 20 25 33 34 26 6 7 4 3 9 22 21 10 12 35 23 36 38 37 39 24 8 12 29 30 adl5386 13 511 1618 15 28 19 27 3231 40 i v 07664-051 quadrature phase splitter tadj c6 0.1f c5 0.1f r8 49.9 ? r4 22.1k ? clpf vdet vdet/vctl vset c7 0.1f c17 open r15 0 ? r23 0 ? c18 open enbl r22 10k ? r2 open c12 1000pf c9 1000pf vmod attin c19 open attout vss1 r11 0 ? r13 0 ? p2 vset r12 0 ? r9 0 ? figure 51. evaluation board schematic table 10. evaluation board configuration options component description default condition vp, gnd power supply and ground clip leads. vp = 5 v, gnd = 0 v r22 device enable. apply either 5 v or 0 v to the sm a connector labeled enbl to enable or disable the iq modulator section of the circuit. if the en bl sma connector is left open, this node is pulled high by r22, enabling the iq modulator. r22 = 10 k r2, c9, c12, c19 modulator vva interconnect. the output of the iq modulator is available at the vmod sma connector. the input and output of the vva ca n be accessed through the attin and attout sma connectors. the iq modulator output can be connected to the vva by installing a 0 resistor at r2 and a 1000 pf capacitor at c19. in this mode, c9 and c12 should be removed. c9, c12 = 1000 pf (0402) r2, c19 = open (0402) r17 to r20, r24 to r29 baseband input filters. these component pads can be used to implement a low-pass filter for the baseband input signals. r17 to r20 = 0 (0402) r24to r29 = open (0402)
adl5386 rev. 0 | page 30 of 36 component description default condition p2 detector controller mode vs. measurement mode. when p2 is installed, the detector operates in standalone measurement mode, measuring the signal strength on the dtin sma connector and providing an output voltage on the vdet and vset sma connectors. to operate the device in agc mode, p2 should be removed, a sample of the output of the vva is connected to dtin (using a directional coupler or a power splitter), and a setpoint voltage should be applied to the vset sma connector. to operate the vva in open-loop mode, disable the detector by connecting tadj to vp. dtin should be ac-coupled to ground, and p2 should be removed. the vva control voltage (0 v to 2 v) is applied to vdet, which becomes an input. the vss1 terminal must be connected to a fixed 2 v source. p2 = installed 07664-052 figure 52. layout of the evaluation board, top layer 07664-053 figure 53. layout of the evaluation board, bottom layer
adl5386 rev. 0 | page 31 of 36 characterization setup detector setup ssb setup figure 55 is a diagram of the characterization test stand setup for the adl5386, which can test the product as a log detector. the hp 8648d signal generator provides the input signal of the detector. all currents and voltages are measured using the agilent 34401a multimeter. figure 54 is a diagram of the characterization test stand setup for the adl5386, which can test the product as a single sideband modulator. the aeroflex ifr 3416 signal generator provides the i and q inputs as well as the lo input. output signals are measured directly using the spectrum analyzer, and currents and voltages are measured using the agilent 34401a multimeter. adl5386 modulator test rack aeroflex ifr 3416 250khz to 6ghz signal generator q out q/am i out i/fm rf output lo output connect to back of unit rf in agilent 34401a multimeter agilent e3631a power supply 6v +? + ? 25v com 5.0000 0.215a 0.215adc freq 100mhz to 4ghz level ? 7dbm bias 0.5v bias 0.5v gain 0.7v gain 0.7v 90 0 qi qp in ip lo qn agnda vp adl5386 50mhz to 2ghz +6dbm vmod 07664-054 rohde & schwartz spectrum analyzer fsu 20hz to 8ghz figure 54. adl5386 characterization board ssb test setup adl5386 detector test rack vp agnda adl5386 vdet/vset dtin hp8648d 9khz to 4000mhz signal generator frequency = 860mhz ?30dbm agilent 34401a multimeter agilent e3631a power supply 6v +? + ? 25v com 5.0000 0.015a 0.015adc agilent 34401a multimeter 1.00 vdc 07664-055 figure 55. adl5386 characterization board detector test setup
adl5386 rev. 0 | page 32 of 36 vva s-paramters setup figure 56 is a diagram of the characterization test stand setup for the adl5386, which can test the product as a vva. the hp 8753d network analyzer measures the s-parameters, while the data precision 8200 sweeps the vctl voltage. currents and voltages are measured using the agilent 34401a multimeter. vva intermodulation test setup figure 57 is a diagram of the characterization test stand setup for the adl5386, which can test the product as a vva. the ifr 2026b provides the two-tone signal to the vva input, the data precision 8200 sweeps the vctl voltage, while the spectrum analyzer measures the output tones of the vva output. currents and voltages are measured using the agilent 34401a multimeter. adl5386 vvas-parameters test rack vp agnda adl5386 vdet attout attin vss1 hp8753d network analyzer data precision 8200 agilent 34401a multimeter agilent e3631a power supply 6v +? + ? 25v com 5.0000 0.004a 2.0000 0.00a 0.004adc 07664-056 figure 56. adl5386 characterization board vva s-parameters test setup adl5386 vva intermod test rack ifr2026b 2.51ghz triple source rohde & schwartz spectrum analyzer fsu 20hz to 8ghz rf in 50mhz to 2ghz +6dbm vp agnda adl5386 vdet attout attin vss1 data precision 8200 agilent 34401a multimeter agilent e3631a power supply 6v +? + ? 25v com 5.0000 0.004a 2.0000 0.00a 0.004 adc 07664-057 figure 57. adl5386 characterization board vva intermodulation test setup
adl5386 rev. 0 | page 33 of 36 outline dimensions 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) compliant to jedec standards mo-220-vjjd-2 072108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 58. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-1) dimensions shown in millimeters ordering guide model temperature range package descript ion package option ordering quantity ADL5386ACPZ-R2 1 C40c to +85c 40-lead lfcsp_vq, 7 tape and reel cp-40-1 250 adl5386acpz-r7 1 C40c to +85c 40-lead lfcsp_vq, 7 tape and reel cp-40-1 750 adl5386-evalz 1 evaluation board 1 1 z = rohs compliant part.
adl5386 rev. 0 | page 34 of 36 notes
adl5386 rev. 0 | page 35 of 36 notes
adl5386 rev. 0 | page 36 of 36 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07664-0-1/09(0)

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